The circuit design for frequency counter is given below by using decade counter (designed by JK flip flops).
The key advantages and benefits if BCD counters areīinary counters can be used to design frequency counters. It is used as divide by 6 counter by supplying pulse at input 1 and grounding reset pins R3 and R4 and connecting QA with input 2.ħ490 IC can work like bi –quinary counter, which is used to store decimal digits in the form of 4 bit binary numbers.Īpplications of BCD Counter or Decade Counters It can also be used as divide by 10 counter by connecting by connecting clock input 2 and QA and connecting all rest pins to ground and giving pulse input to 1. This 7490 IC has inbuilt Divide by 2 and Divide by 5 counters in it.
If the pins R3 & R4 are high, then the count on QA, QB, QC and QD is 1001.Īs we studied earlier, we can increase the counting capability of a Decade number by connecting more ICs n series we can count 99 with two 7490 ICs connected in series. If any one of R1 & R2 is at high or R3 & R4 are at ground, the counter will reset all the outputs QA, QB, QC and QD to 0.
The Mod of the IC 7490 is set by changing the RESET pins R1, R2, R3, R4. When the count reaches 10, the binary output is reset to 0 (0000), every time and another pulse starts at pin number 9. As it is a 4 bit binary decade counter, it has 4 output ports QA, QB, QC and QD. It is a simple counter which can count from 0 – 9. The IC 74LS90 is one most used chip we use to design decade counter. The other commonly available integrated circuits (ICs) for Decade counter and their purposes are listed below. Commonly available Decade counter IC’sĤ017B and 7049 are the most used ICs to design a decade counter. There are several types of counters available, like Mod 4 counter, Mod 8 counter, Mod 16 counter and Mod 5 counters etc. The Mod n counter can calculate from 0 to 2n-1. If a counter resets itself after counting n bits is called “Mod- n counter” “Modulo- n counter”, where n is an integer. The number that a counter circuit can count is called “Mod” or “Modulus”. Multiple counters are connected in series, to count up to any desired number. The count starts from 0000 (zero) to 1001 (9) and then the NAND gate will reset the circuit. So it is capable of counting 16 bits or 16 potential states, in which only 10 are used. If we observe the decade counter circuit diagram, there are four stages in it, in which each stage has single flip flop in it.
The state diagram of Decade counter is given below. After count 10, the logic gate NAND will trigger its output from 1 to 0, and it resets all flip flops. The count is decoded by the inputs of NAND gate X1 and X3. The NAND gate output is zero when the count reaches 10 (1010). It represents the count of circuit for decimal count of input pulses. The above table describes the counting operation of Decade counter. This means the pulse after count 9 will again start the count from count 0. The NAND gate output is connected to clear input, so it resets all the flip flop stages in decade counter. As we know that for high inputs, the NAND gate output will be low. The next clock pulse advances to count 10 (1010). The first clock pulse can make the circuit to count up to 9 (1001). When we connect a clock signal input to the counter circuit, then the circuit will count the binary sequence. This is first stage of the counter cycle. When the Decade counter is at REST, the count is equal to 0000. This ripple counter can count up to 16 i.e. The output of the NAND gate is connected in parallel to the clear input ‘CLR’ to all the flip flops. The clock input of every flip flop is connected to the output of next flip flop, except the last one. The J output and K outputs are connected to logic 1. The above figure shows a decade counter constructed with JK flip flop. There are some available ICs for decade counters which we can readily use in our circuit, like 74LS90. As it can go through 10 unique combinations of output, it is also called as “Decade counter”.